This application claims priority to Korean Patent Application No. 2001-59040, filed on Sep. 24, 2001, which is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a reduced chip select output time (tco) from the time when an externally inputted chip select signal transitions from an inactive state to an active state, to the time when valid data is loaded on a data bus.
In general, a static random access memory (SRAM) is controlled by an external chip select signal referred to herein as /XCS. When the external chip select signal /XCS is inactive, the SRAM is in a standby mode to hold data stored therein When the external chip select signal /XCS is active, the SRAM reads/writes data from/to a memory cell, which is assigned by an address. Further, signals for pre-charging bitlines of a memory cell, or equalizing or driving a sense amplifier, are also influenced by the external chip select signal /XCS. Only in a case where a chip select signal /CS is in an enable state where a row address signal or a column address signal transitions, are bitline pre-charge signals, or a sense amplifier equalizing and driving signal, generated to perform an abnormal write/read operation.
FIG. 1 schematically illustrates an architecture of a conventional SRAM. SRAM 1 comprises a memory cell array 30 having a plurality of memory cells MCs located at intersections of rows and columns. In the memory cell array 30, wordlines WL are provided to corresponding rows of memory cells and a pair of bitlines (BL, /BL) are provided to corresponding columns of memory cells. A target memory cell for reading and writing data is selected according to combinations of signal levels of address signals A0-An.
The SRAM 1 further comprises control logic 50 for controlling read/write operations of the SRAM 1 according to externally inputted signals, i.e., an external chip select signal /XCS, a write enable signal /WE, a read enable signal /RE, or other control signals (not shown). The control logic 50 generates an internal chip select signal /CS for activating an address input buffer 10 in response to the external chip select signal /XCS.
The address input buffer 10 is activated in response to the internal chip select signal /CS, receives the address signals A0-An from an address input terminal (not shown), and transfers internal address signals IA0-IAn to an address decoder 20 and the control logic 50.
The address decoder 20 comprises a row decoder 20 and a column, decoder 22. The row decoder 21 receives a part of address signals IA0-IAn from the address input buffer 10, and activates a wordline corresponding to inputted address signals. The column decoder 22 connects a pair of bitlines corresponding to all the other address signals excluding the address signals inputted to the row decoder 21, to a sense amplify and write driver 40.
In response to control signals PSA and PEQ from the control logic 50, the sense amplify and write driver 40 writes/reads data to/from a memory cell that is coupled to a bitline corresponding to address signals from the column decoder 22.
A data input/output buffer 60 is coupled to the sense amplify and write driver 40 through a pair of data input/output lines (IO, /IO). The input/output buffer 60 transfers data between a data input/output terminal (not shown) and the sense amplify and write driver 40. Data inputted from the data input/output terminal through a data bus, is transferred to the sense amplify and write driver 40 through the input/output buffer 60 and a pair of data input/output lines IO, /IO. Data read-out from the sense amplify and write driver 40 is outputted to the data input/output terminal through the pair of input/output lines IO and /IO, the data input/output buffer 60, and the data bus 70.
The control logic 50 receives the address signals IA0-IAn from the address input buffer 10, and outputs pulse signals PWL, PSA, PEQ, and MMX, which are needed to perform a write/read operation when the address signals IA0-IAn transition. For example, the pulse signal PWL is a signal for enabling the row decoder 21, the pulse signal PSA is a signal for driving the sense amplify and write driver 40, the pulse signal PEQ is a signal for equalizing the sense amplify and write driver 40, and the pulse signal PMX is a signal for driving the data input/output buffer 60.
FIG. 2 illustrates an architecture of the control logic 50 of the SRAM 1 shown in FIG. 1. The control logic 50 comprises a chip select buffer 51, a short pulse generation circuit 52, an address transition detect (ATD) circuit 53, and a pulse generation circuit 54. The chip select buffer 51 generates an internal chip select signal /CS for activating the address buffer 10, and a control signal /CSATD for activating the address transition detect circuit 53 in response to an external chip select signal /XCS. The short pulse generation circuit 52 receives the address signals IA0-IAn from the address input buffer 10 to generate short pulse signals SP0-SPn when the address signals IA0-IAn transition. The address transition detect circuit 53 summates the short pulse signals SP0-SPn from the short pulse generation circuit 52 to generate an address transition detect signal ATD in response to the control signal /CSATD. The pulse generation circuit 54 generates a series of pulse signals PWL, PSA, PEQ, and PMX, which are needed to start a write/read operation in response to the address transition detect signal ATD.
FIG. 3 illustrates an architecture of the chip select buffer 51. The chip select buffer 51 comprises a NOR gate 101, inverters 102-104, a delay unit 105, and a NAND gate 106.
The NOR gate 101 has input terminals and an output terminal. The input terminals receive the external chip select signal /XCS and a signal of a ground voltage level (i.e., logic xe2x80x9c0xe2x80x9d). The inverters 102-104 are sequentially coupled between the output terminal of the NOR gate and a chip select output terminal /CS in cascade. Therefore, when the external chip select signal /XCS transitions from high to low, the internal chip select signal /CS becomes active at a high level.
The delay unit 105 delays an output signal from the output terminal of the NOR gate 101 by a predetermined time. The NAND gate 106 has input terminals and an output terminal. The input terminals of the NAND gate 106 receive an output signal from the output terminal of the NOR gate 101 and a signal delayed by the delay unit 105. The output terminal of the NAND gate 106 outputs a control signal /CSATD for controlling the address transition detect circuit 53. Thus, if the external chip select signal /XCS is maintained in low level for a longer time than a delay time of the delay unit 105, the control signal /CSATD becomes active at the high level.
FIG. 4 illustrates architectures of the address input buffer 10 and the short pulse generation circuit 52. The address input buffer 10 comprises NOR gates 110-112 each corresponding to their externally inputted address signals A0-An. Each of the NOR gates 110-112 receives the internal chip select signal /CS and a corresponding address signal to carry out a NOR operation.
FIG. 5 illustrates an architecture of the address transition detect circuit 53 shown in FIG. 2. The address transition detect circuit 53 comprises a PMOS transistor 131, inverters 132, 134, and 138, a latch 140, a NOR gate 133, an NMOS transistor 137, and N of NMOS transistors 150-152. The PMOS transistor 131 has a current path formed between a power supply voltage and a first node N1 with a control gate. The latch 140 comprises inverters 135 and 136, and has one end coupled to the first node and the other end. The inverter 134 has an input terminal coupled to the other end of the latch 140 and an output terminal. The NOR gate 133 has input terminals for receiving the control signal /CSATD and an output terminal. The inverter 132 has an input terminal coupled to the output terminal of the NOR gate 133 and an output terminal coupled to the control gate of the PMOS transistor 131. The NMOS transistor 137 has a current path between the first node N1 and a ground voltage with a control gate controlled by the control signal /CSATD. Each of the NMOS transistors 150-152 has a current path formed between the first node N1 and the ground voltage with a gate controlled by a corresponding one of signals SP0-SPn outputted from the signal pulse generation circuit 52. The inverter 138 has an input terminal coupled to the first node N1 and an output terminal for outputting an address transition detect signal ATD.
The address transition detect circuit 53 detects whether an address transitions or not, by performing an OR operation for the signals SP0-SPn from the short pulse generation circuit 52 when the control signal /CSATD is active at a low level. Specifically, when at least one of the signals SP0-SPn from the short pulse generation circuit 52 is in a high level, among the NMOS transistors 150-152, an NMOS transistor corresponding to the signal of the high level is turned on. Thus, the address transition detect signal ATD becomes high. On the other hand, when the short pulse signals SP0-SPn from the short pulse generation circuit 52 are low, the NMOS transistors 150-152 are turned off. When the control signal /CSATD is inactive at the high level, the NMOS transistor 137 is turned on so that the first node becomes low and thus the address transition detect signal ATD is high.
FIG. 6A illustrates operation timings of the control signals shown in FIG. 2 during an address access time tAA, that is counted from the time when an address signal transitions to the time when valid data is loaded on a data bus 70.
Referring to FIG. 2 and FIG. 6A, when the external chip select signal /XCS is maintained in an active state of a low level, the chip select signal /CS and the control signal /CSATD outputted from the chip select buffer 51 are maintained in the active state of the low level, respectively. If one IAi of the address signals IA0-IAn from the address input buffer 10 transitions, the short pulse generation circuit 52 outputs as a short pulse signal a signal SPi corresponding to the transitioned address signal Iai.
If at least one of the output signals SP0-SPn from the short pulse is the short pulse signal of the high level, the address transition detect circuit 53 outputs an address transition detect signal ATD having the same shape as that of the short pulse signal SPi. The pulse generation circuit 54 generates a series of pulse signals PWL, PSA, PEQ, and PMX when the address transition detect signal ATD transitions from high to low. The decoder 20 and the sense amplify and write driver 40 carry out a write/read operation in response to the series of the pulse signals PWL, PSA, PEQ, and PMX, which are generated from the pulse generation circuit 54. Among the pulse signals, only the pulse signal PWL is exemplarily illustrated in FIG. 6A.
FIG. 6B illustrates operation timings of the control signals shown in FIG. 2 during a chip select output time (tco), which is counted from the time when the external chip select time /XCS transitions from the high to the low, to the time when valid data is loaded on the data bus 70.
Referring to FIG. 2 and FIG. 6B, as the external chip select signal /XCS becomes active from high to low, the chip select buffer 51 outputs a chip select signal /CS of a low level. The NOR gate 101 and the inverters 102-104 of the chip select buffer 51, shown in FIG. 3, cause a delay time t1, which is counted from the time when the external chip select signal /XCS transitions from high to low, to the time when the chip select signal /CS from the chip select buffer 71 transitions from high to low. Due to a delay time of the delay unit 105, the control signal /CSATD becomes active at the low a good while after activating the external chip select signal /XCS.
The address input buffer 10 receives externally inputted address signals A0-An in response to the chip select signal /CS. The short pulse generation circuit 52 outputs signals SP0-SPn according to the transition of address signals IA0-IAn outputted from the address input buffer 10. Further, the address transition detect circuit 53 does not output an address transition detect signal ATD of a low level until the control signal /CSATD is made active at the low and a short pulse signal SPi outputted from the address buffer 20 transitions from high to low. As a result, the address access time tAA is shorter than the chip select output time (tco), which is counted from the time when the external chip select signal /XCS becomes active at the low to the time when the valid data is loaded on the data bus 70 as the series of the pulse signals PWL, PSA, PEQ, and PMX are generated.
With respect to both the address access time TAA and the chip select output time (tco) in a design of the conventional SRAM 1, the address transition detect circuit 53 detects whether a short pulse signal exists among the signals SP0-SPn outputted from the short pulse generation circuit 52. Afterwards, if the address transition detect circuit 53 outputs the detect signal ATD, the pulse generation circuit 54 operates in response to the detect signal ATD.
Therefore, as previously mentioned, the chip select output time (tco) reflects the time t1 required for activating the internal chip select signal /CS to make the chip select buffer 51 activate the address input buffer 10 when the external chip select signal /XCS transitions from an inactive state to an active state. As a result, the chip select output time (tco) becomes longer than the address access time tAA by the time t1.
In a semiconductor memory device, the chip select output time (tco) is regulated to be equal to the address access time tAA. As discussed above, however, the chip select output time (tco) is comparatively longer than the address access time tAA. For the reasons, the short address access time tAA in a conventional semiconductor memory device should be increased to be equal to the chip select output time (tco). As a result, the whole access speed of the conventional semiconductor memory device is decreased and a new scheme has been required to improve the chip select output time (tco) for increasing the access speed.
The present invention is generally directed to an improved semiconductor memory device that produces a reduction in the total access time by shortening a chip select output time.
According to one embodiment of the invention, a semiconductor memory device, which inputs/outputs data in response to an external chip select signal and an address signal that are inputted through signal input terminals, comprises a memory cell array for storing data, a write/read circuit for writing/reading the data to/from the memory cell array, a first input circuit for transferring the address signal to the write/read circuit through the signal input terminal in response to a first control signal, and a control logic for detecting whether the address signal inputted to the first input circuit transitions to generate a series of pulse signals so that the write/read circuit writes/reads a data signal.
Preferably, the control logic comprises a second input circuit, a detect circuit, pulse enable control circuit, a pulse generation circuit. The second input circuit receives the external chip select signal, and activates the first control signal and a second control signal when the external chip select signal is active. The detect circuit outputs an address transition detect signal when the second control signal is active and the address signal, which is outputted to the first input circuit, transitions. The pulse enable control circuit activates a pulse enable signal in response to the address transition detect signal when the first control signal is active, and activates the pulse enable signal when the first control signal transitions from an inactive state to an active state. The pulse generation circuit generates a series of the pulse signals in response to the pulse enable signal.
In another aspect of the invention, the pulse enable control circuit comprises a control signal generation circuit for activating a third control signal when it is sensed that the first control signal transitions from an inactive state to an active state. The control signal generation circuit further generates a pulse enable signal for activating the pulse enable signal when the third control signal is active and for activating the pulse enable signal in response to the address transition detect signal when the third control signal is inactive. Preferably, the first control signal is logic xe2x80x9c1xe2x80x9d in the active state and is logic xe2x80x9c0xe2x80x9d in the inactive state.
In another aspect, the control signal generation circuit comprises a first inverter for receiving the first control signal, a first delay circuit for receiving and delaying for a first delay time an output signal from the first inverter, a second delay circuit for receiving and delaying for a second delay time an output signal from the first delay circuit, a second inverter for receiving an output signal from the second delay circuit, and a NAND gate for receiving output signals form the second inverter and the first delay circuit to output a third control signal.
In yet another aspect, the pulse enable circuit comprises a NAND gate for receiving the third control signal from the NAND gate of the control signal generation circuit and the address transition detect signal from the detect circuit, and an inverter for receiving an output signal from the NAND gate of the pulse enable signal and outputting the pulse enable signal.
In another aspect of the invention, the detect circuit comprises a short pulse generation circuit for generating a short pulse signal when the address signal inputted to the first input circuit transitions, and an address transition detect circuit for outputting the address transition detect signal when the second control signal is active and the short pulse signal is inputted from the short pulse generation circuit. When the address signal inputted to the first input circuit is plural, the detect circuit outputs the address transition detect signal when at least one of the plural address signals inputted to the first input circuit transitions.
According to another embodiment of the invention, a semiconductor memory device, which inputs/outputs data in response to an external chip select signal and an address signal that are inputted through signal input terminals, comprises a memory cell array for storing data, a write/read circuit for writing/reading the data to/from the memory cell array, a first input circuit for transferring the address signal inputted through the signal input terminal to the write/read circuit in response to a first control signal, and a control logic for detecting whether the address signal inputted to the first input circuit transitions to generate a series of pulse signals so that the write/read circuit writes/reads a data signal.
Preferably, the control logic comprises a second input circuit for receiving the external chip select signal and outputting the first control signal and a second control signal in response to the external chip select signal, a short pulse generation circuit for generating a short pulse signal when the address signal inputted to the first input circuit transitions, and a pulse generating means for generating a series of pulse signals when the second control signal is active and the short pulse signal is inputted from the short pulse generation circuit and for generating the series of the pulse signals when the second control signal transitions form an inactive state to an active state.
In yet another aspect, the pulse generating means comprises a control signal generation circuit for activating a third control signal when it is sensed that the first control signal transitions from an inactive state to an active state, a chip select control circuit for outputting the short pulse signal from the short pulse generation circuit as a chip select short pulse signal when the third control signal is inactive and the short pulse signal is inputted from the short pulse generation circuit and for masking and then outputting an output signal from the short pulse generation circuit as the chip select short pulse signal, an address transition detect circuit for outputting the chip select short pulse signal from the chip select control circuit as the address transition detect signal in response to the second control signal, and a pulse generation circuit for generating the series of the pulse signals in response to the address transition detect signal.
These and other aspects, object, feature and advantages of the present invention will be described or become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.